1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming double gated field effect transistors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) One of the fundamental parameters of FET design is the threshold voltage (Vt). The threshold voltage of a FET is generally defined as the gate voltage required to switch the transistor on or off (depending upon the type of FET). FETs with different threshold voltages have different operational characteristics. For example, transistors with lower threshold voltage generally can operate at higher operational frequency, and have a higher current drive. However, transistors with lower threshold voltage also have higher leakage current, and thus generally use more power than transistors with higher threshold voltages.
Thus, in some applications it is generally desirable to have transistors with lower threshold voltages to improve performance, while in other applications it is generally desirable to have transistors with higher threshold voltage to reduce unwanted power consumption. Unfortunately, it is generally difficult to make transistors with different threshold voltage on the same device when the transistors employ ultra-thin bodies.
This is especially true of double gated field effect transistors. Double gated FETs use two gates, one on each side of the body, to facilitate scaling of CMOS dimensions while maintaining an acceptable performance. In particular, the use of the double gate increases the control of the gate on the channel potential, which allows the transistor to have better current control, without increasing the gate length of the device. As such, the double gated FET is able to have the current control of a larger transistor without requiring the device space of the larger transistor.
Thus, there is a need for improved device structures and methods of fabrication of double gated transistors that provide transistors having different threshold voltages on the same device without overly increasing fabrication complexity.
Accordingly, the present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. In a first aspect, the invention is a method for forming a plurality of transistors having different threshold voltages, the method comprising the steps of:
a) providing a semiconductor substrate;
b) forming a plurality of shapes on the semiconductor substrate, each of the plurality of shapes having a width;
c) selectively adjusting the widths of at least one selected shapes;
d) patterning the semiconductor substrate using the plurality of shapes to form a plurality of transistor bodies such that the width of each the plurality of transistor bodies is at least partially determined by the width of a corresponding one of the plurality of shapes;
e) providing a first gate structure of a first work-function adjacent a first body edge of each of the plurality of transistor bodies; and
f) providing a second gate structure of a second work-function adjacent a second body edge of each of the plurality of transistor bodies.
In a second aspect, the invention is a plurality of transistors comprising:
a) a plurality of transistor bodies formed on a substrate, the transistor bodies each having a first vertical edge and a second vertical edge defining a transistor body width, wherein a selected portion of the plurality of transistor bodies has an adjusted width;
b) a plurality of first gate structures, each of the plurality of first gate structures adjacent to one of the plurality of transistor body first vertical edges, the plurality of first gate structures having a first work-function; and
c) a plurality of second gate structures, each of the plurality of second gate structures adjacent to one of the plurality of transistor body second vertical edges, the plurality of second gate structures having a second work-function.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.